1. Field of the Invention
The present invention relates to a stacked semiconductor chip package and more particularly to a semiconductor chip package and a fabrication method thereof for packaging a plurality of stackable-type semiconductor chips into a single semiconductor chip package.
2. Description of the Conventional Art
A semiconductor chip package in which a single semiconductor chip is packaged is generally known, and a small outline J-leaded (SOJ) semiconductor chip package is one of several types thereof.
With reference to FIG. 1, a SOJ semiconductor chip package is provided such that a semiconductor chip 1 is fixed to a paddle 3 of a lead frame (not shown) by an insulating adhesive or paste. Pads (not shown) of the semiconductor chip 1 are electrically connected with corresponding internal leads 2 by conductive wires 4. A package body 6 is formed by using material 5 to seal the semiconductor chip 1, the internal leads 2 and the conductive wires 4. Finally, external leads 2 are extended from the internal leads 2 to an exterior of the package body 6, each external lead 2 being formed in a xe2x80x98Jxe2x80x99 shape.
However, according to the conventional art, since only a single semiconductor chip is packaged in the semiconductor chip package, when mounting the package on a printed circuit board, an area occupied by the package on the board is always uniform which results in deterioration of the efficiency thereof.
Accordingly, the present invention is directed to a semiconductor chip package which obviates problems and disadvantages present in the conventional art.
An object of the present invention is to provide a semiconductor chip package in which a plurality of semiconductor chips are packaged to improve integration thereof.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor chip package includes: a substrate having first and second conductive pads provided on an upper surface and a lower surface thereof, respectively; a first semiconductor chip attached to the upper surface of the substrate; first conductive wires for electrically connecting the first semiconductor chip to the first conductive pads; a plurality of leads attached to both end portions of the substrate; a first molding part for sealing the substrate, the first semiconductor chip and the first conductive wires; a second semiconductor chip attached on an upper surface of the first molding part; second conductive wires for connecting the second semiconductor chip with the plurality of leads; and a second molding part for sealing the second semiconductor chip, the second conductive wires and a portion of each of the leads.
In addition, to achieve the above object of the present invention, there is provided a method for fabricating a semiconductor chip package which includes: attaching first conductive pads to an upper surface of a substrate in which a circuit is provided; attaching second conductive pads to a lower surface of the substrate; attaching a first semiconductor chip to the upper surface of the substrate; electrically connecting the first semiconductor chip to the first conductive pads; providing a plurality of leads at both end sides of the substrate; forming a first molding part by sealing the first semiconductor chip and the substrate; attaching a second semiconductor chip to an upper surface of the first molding part; electrically connecting the second semiconductor chip to the leads; and forming a second molding part by sealing the second semiconductor chip and a portion of each of the leads.
Here, the substrate may have first conductive pads provided on an upper surface thereof, second conductive pads provided at a lower surface thereof, an opening, and connection means provided at profiles of the opening for electrically connecting the first conductive pads to the corresponding second conductive pads.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide and further explanation of the invention as claimed.